One embodiment of the present invention relates to memory devices. In particular, one embodiment of the present invention relates to a synchronously controlled global controller for memory devices.
Memory structures or devices have become integral parts of modern VLSI systems, including digital line processing systems. Although typically it is desirable to incorporate as many memory cells as possible into a given area of a memory structure, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints may impose severe limitations upon memory structure designs, which traditional memory structures and subcomponent implementations may fail to obviate.
A certain amount of time is needed to complete a read or write operation in such memory structures. After the read or write operation is complete, additional time is needed to recharge the signals. The minimum cycle time is achieved if pre-charging starts right after completion of the read or write operation. However, there is no signal indicating the completion of the read or write operation. As a result, pre-chargers are generally fired at the falling edge of a clock pulse, so that the write or read operations must be completed in the first half of the cycle when the clock pulse is high. In other words the clock pulse must remain high long enough for the read and write operations to finish. In the second half of the cycle, when clock is low, the pre-chargers precharge
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.